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ir s2453(1)d(s) 1 www.irf.com ? 20 12 international rectifier november 28 , 2012 features ? integrated 600 v full - bridge gate driver ? ct, rt programmable oscillator ? 15.6 v zener clamp on v cc ? micropower startup ? logic level latched shutdown pin ? non - latched shutdown on ct pin (1/6th v cc ) ? internal bootstrap fets ? excellent latch immunity on all inputs & outputs ? esd protection on all pins ? 14 - lead soic or pdip package ? 0.5 or 1.0 s (typ.) internal dead time ? rohs compliant product summary topology full - bridge v offset 600 v i o+ & i o - (typical) 180 ma & 260 ma deadtime (typical) 1.0 s (IRS2453D) 0.5 s (irs24531d) package options 14 lead pdip 14 lead soic IRS2453Dpbf (narrow body) irs2453(1)dspbf ordering information base part number package type standard pack complete part number form quantity IRS2453D(s) pdip14 tube/bulk 25 IRS2453Dpbf soic14n tube/bulk 55 IRS2453Dspbf tape and reel 2500 IRS2453Dstrpbf irs24531ds soic14n tube/bulk 55 irs24531dspbf tape and reel 2500 irs24531dstrpbf
ir s2453(1)d(s) 2 www.irf.com ? 20 12 international rectifier november 28 , 2012 table of contents page ordering information 1 description 3 typical connection diagram 3 qualification information 4 absolute maximum ratings 5 recommended operating conditions 6 recommended component values 6 electrical characteristics 7 functional block diagram 9 input / output pin equivalent circuit diagram 10 lead definitions 11 lead assignments 11 application information and additional details 12 package details 15 tape and reel details 16 part marking information 17
ir s2453(1)d(s) 3 www.irf.com ? 20 12 international rectifier november 28 , 2012 description the irs2453(1)d is based on the popular ir2153 self - oscillating half - bridge gate driver ic, and incorporates a high voltage full - bridge gate driver with a front end oscillator similar to the industry standard cmos 555 timer. hvic and latch immune cmos technologies enable ruggedized monolithic construction. the output driver features a high pulse current buffer stage designed fo r minimum driver cross - conduction. noise immunity is achieved with low di/dt peak of the gate drivers, and with an under voltage lockout hysteresis greater than 1.5 v. the irs2453(1)d also includes latched and non - latched shutdown pins. typical connection diagram l o a d 1 4 1 3 1 2 1 1 1 0 9 8 1 2 3 4 5 6 7 i r s 2 4 5 3 ( 1 ) d v c c c t r t l o 1 l o 2 s d v b 1 h o 1 v s 1 v b 2 h o 2 v s 2 c o m n c + a c r e c t i f i e d l i n e - a c r e c t i f i e d l i n e 1 5 v
ir s2453(1)d(s) 4 www.irf.com ? 20 12 international rectifier november 28 , 2012 qualification information ? qualification level industrial ?? comments: this family of ics has passed jedecs industrial qualification. irs consumer qualification level is granted by extension of the higher industrial level. moisture sensitivity level soic14 msl2 ??? 260c (per ipc/jedec j - std - 020) pdip14 not applicable (non - surface mount package style) esd machine model class c (per jedec standard jesd22 - a115) human body model class 2 (per eia/jedec standard eia/jesd22 - a114) ic latch - up test class i, level a (per jesd78) rohs compliant yes ? qualification standards can be found at international rectifiers web site http://www.irf.com/ ?? higher qualification ratings may be available should the user have such requirements. please contact your international rectifier sales representative for further information. ??? higher msl ratings may be available for the specific package types listed here. please contact your international rectifier sales representative for further information.
ir s2453(1)d(s) 5 www.irf.com ? 20 12 international rectifier november 28 , 2012 absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage parameters are absolute voltages referenced to com, all currents are defined positive into any lead. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. symbol definition min. max. units v b1, v b2 high side floating supply voltage - 0.3 625 v v s1, v s2 high side floating supply offset voltage v b - 25 v b + 0.3 v ho1 , v ho2 high side floating output voltage v s - 0.3 v b + 0.3 v lo1 , v lo2 low side output voltage - 0.3 v cc + 0.3 v rt r t pin voltage - 0.3 v cc + 0.3 v ct c t pin voltage - 0.3 v cc + 0.3 v sd sd pin voltage - 0.3 v cc + 0.3 i rt r t pin current - 5 5 ma i cc supply current ( ? s /dt allowable offset voltage slew rate - 50 50 v/ns p d maximum power dissipation @ t a a ja thermal resistance, junction to ambient, 8 - pin dip --- 125 oc/w r ja thermal resistance, junction to ambient, 8 - pin soic --- 200 t j junction temperature - 55 150 oc t s storage temperature - 55 150 t l lead temperature (soldering, 10 seconds) --- 300 ? this ic contains a zener clamp structure between the chip v cc and com which has a nominal breakdown voltage of 15.6 v. please note that this supply pin should not be driven by a dc, low impedance power source greater than the v clamp specified in the electrical characteristics section.
ir s2453(1)d(s) 6 www.irf.com ? 20 12 international rectifier november 28 , 2012 recommended operating conditions for proper operation the device should be used within the recommended conditions. symbol definition min. max. units v bs1, v bs2 high side floating supply voltage v cc - 0.7 v clamp v v s1 , v s2 steady state high side floating supply offset voltage - 3.0 ( ? ccuv+ v clamp i cc supply current ( ? ? ? s node would decrease v s below ground by more than - 5v. ? ? recommended component values symbol component min. max. units r t timing resistor value 1 --- k ? c t c t pin capacitor value 330 --- pf vbias (vcc, vbs) = 14 v, vs=0 v and ta = 2 5 c, clo1=clo2 = cho1=cho2 = 1 nf. irs2453(1)d frequency vs. rt irs2453(1)d frequency vs. rt
ir s2453(1)d(s) 7 www.irf.com ? 20 12 international rectifier november 28 , 2012 electrical characteristics v bias (v cc , v bs ) = 14 v, c t = 1 nf and t a = 25 c unless otherwise specified. the v o and i o parameters are referenced to com and are applicable to the respective output leads: ho or lo. clo1=clo2=cho1=cho2=1nf. symbol definition min typ max units test conditions low voltage supply characteristics v ccuv + rising v cc under voltage lockout threshold 10.0 11.0 12.0 v v ccuv - falling v cc under voltage lockout threshold 8.0 9.0 10.0 v ccuvh ys v cc under voltage lockout hysteresis 1.5 2.0 2.4 i qccuv micropower startup v cc supply current --- 140 200 a v cc ? cc supply current --- 1.3 2.0 ma i cc_20k v cc supply current at f osc (r t = 36.5 k) ccflt v cc supply current when sd > v sd --- 360 500 a v clamp v cc zener clamp voltage 14.6 15.6 16.6 v i cc = 5 ma floating supply characteristics i qbs1uv, i qbs2uv micropower startup v bs supply current --- 3 10 a v cc ? v bs1uv+, v bs2uv + v bs supply under voltage positive going threshold 8.0 9.0 10.0 v v bs1uv - , v bs2uv - v bs supply under voltage negative going threshold 7.0 8.0 9.0 i lk1, ilk2 offset supply leakage current --- --- 50 ? oscillator i/o characteristics f osc oscillator frequency 19.6 20.2 20.8 khz r t = 36.5 k ? ? o < 100 khz i ct c t pin current --- 0.05 1.0 ? cc = 7 v v ct+ upper c t ramp voltage threshold --- 9.3 --- v v ct - lower c t ramp voltage threshold --- 4.7 --- v rt+ high level r t output voltage, v cc - v rt --- 10 50 mv i rt = 100 ? ? ? ? ? ? ?
ir s2453(1)d(s) 8 www.irf.com ? 20 12 international rectifier november 28 , 2012 electrical characteristics v bias (v cc , v bs ) = 14 v, c t = 1 nf and t a = 25 c, unless otherwise specified. the v o and i o parameters are referenced to com and are applicable to the respective output leads: ho or lo. clo1=clo2=cho1=cho2=1 nf. symbol definition min typ max units test conditions gate driver output characteristics v oh high level output voltage, v bias - v o --- v cc --- v i o = 0 a v ol low level output voltage, v o --- com --- v ol_uv uv - mode output voltage, v o --- com --- i o = 0 a , v cc ? r output rise time --- 120 200 ns t f output fall time --- 50 100 t sd shutdown propagation delay --- 250 --- t d output dead time (ho or lo) IRS2453D 0.8 1.0 1.40 ? o+ output source current --- 180 --- ma i o - output sink current --- 260 --- shutdown v sd shutdown threshold at sd pin (latched) 1.8 2.0 2.3 v v ctsd c t voltage shutdown threshold (non - latched) 2.2 2.3 2.5 v rtsd sd mode r t output voltage, v cc - v rt --- 10 50 mv i rt = 100 ? ? ct = 0 v --- 100 300 i rt = 1 ma, r t = 14 k ? ct = 0 v bootstrap fet characteristics v b1_on v b2_on v b when the bootstrap fet is on 13.7 14.0 --- v i b1_cap i b2_cap v b source current when fet is on 40 55 --- ma c bs =0.1 f b1_10 v i b2_10 v v b source current when fet is on 10 12 --- v b =10 v
ir s2453(1)d(s) 9 www.irf.com ? 20 12 international rectifier november 28 , 2012 functional block diagram vb1 pulse gen delay pulse filter lo1 vs1 r s q ct rt r q s q ho1 - - - + + + r r r/2 r/2 vb2 pulse gen delay hv level shift vcc pulse filter lo2 vs2 com r s q 15.4v ho2 sd 2.0v uv detect dead time s r q dead time r1 s q r2 bootstrap drive 4 3 5 2 7 1 8 9 10 6 12 13 14 hv level shift bootstrap drive q
ir s2453(1)d(s) 10 www.irf.com ? 20 12 international rectifier november 28 , 2012 input / output pin equivalent circuit diagrams: v c c c o m l o 1 e s d d i o d e e s d d i o d e v b 1 v s 1 h o 1 e s d d i o d e e s d d i o d e 2 5 v 2 5 v 6 0 0 v v c c c o m l o 2 e s d d i o d e e s d d i o d e v b 2 v s 2 h o 2 e s d d i o d e e s d d i o d e 2 5 v 2 5 v 6 0 0 v v c c c o m s d e s d d i o d e e s d d i o d e r e s d v c c e s d d i o d e e s d d i o d e 2 5 v v c c c o m c t e s d d i o d e e s d d i o d e r e s d
ir s2453(1)d(s) 11 www.irf.com ? 20 12 international rectifier november 28 , 2012 lead definitions pin symbol description 1 vcc logic and internal gate drive supply voltage 2 com ic power and signal ground 3 ct oscillator timing capacitor input 4 rt oscillator timing resistor input 5 sd shutdown input 6 lo1 low side gate driver output 7 lo2 low side gate driver output 8 vs2 high voltage floating supply return 9 ho2 high side gate driver output 10 vb2 high side gate driver floating supply 11 nc no connect 12 vs1 high voltage floating supply return 13 ho1 high side gate driver output 14 vb1 high side gate driver floating supply lead assignment 14 13 12 11 10 9 8 1 2 3 4 5 6 7 i r s 2 4 5 3 ( 1 ) d ( s ) vcc ct rt lo 1 lo 2 sd vb 1 ho 1 vs 1 vb 2 ho 2 vs 2 com nc
ir s2453(1)d(s) 12 www.irf.com ? 20 12 international rectifier november 28 , 2012 application information and additional details timing diagram d t d t 1 / 3 v c c 2 / 3 v c c v c c v c c u v + l o 1 v c c l o 2 v c c 1 / 6 v c c v r t v c c i r t - 1 m a 1 m a v c c v c c h o 1 h o 2 d t fault mode vct<1/6*vcc
ir s2453(1)d(s) 13 www.irf.com ? 20 12 international rectifier november 28 , 2012 functional description under - voltage lock - out mode (uvlo) the under - voltage lockout mode (uvlo) is defined as the state the ic is in when v cc is below the turn - on threshold of the ic. the irs2453(1)d under - voltage lock - out is designed to maintain an ultra low supply current of e the high and low side output drivers are activated. during under - voltage lock - out mode, the high and low side driver outputs lo1, lo2, ho1, ho2 are all low. with v cc above the v ccuv+ threshold, the ic turns on and the output begin to oscillate. normal operating mode once v cc reaches the start - up threshold v ccuv+ , the mosfet m1 opens, rt increases to approximately v cc (v cc - v rt+ ) and the external ct capacitor starts charging. once the ct voltage reaches v ct - (about 1/3 of v cc ), established by an internal resistor ladder, lo1 and ho2 turn on with a delay equivalent to the dead time (t d ). once the ct voltage reaches v ct+ (approximately 2/3 of v cc ), lo1 and ho2 go low, rt goes down to approximately ground (v rt - ), the ct capacitor starts discharging and the d ead time circuit is activated. at the end of the dead time, lo2 and ho1 go high. once the ct voltage reaches v ct - , lo2 and ho1 go low, rt goes to high again, the dead time is activated. at the end of the dead time, lo1 and ho2 go high and the cycle starts over again. the frequency is best determined by the graph, frequency vs. rt, page 3, for different values of ct. a first order approximate of the oscillator frequency can also be calculated by the following formula: this equation can vary slightly from actual measurements due to internal comparator over - and under - shoot delays. bootstrap mosfet the internal bootstrap fet and supply capacitor (c boot ) comprise the supply voltage for the high side driver circuitry. th e internal boo t strap fet only turns on when the corresponding lo is high. to guarantee that the high - side supply is charged up before the first pulse on ho1 and ho2, lo1 and lo2 outputs are both high when ct ramps between zero and 1/3*v cc . lo1 and lo2 are also high when ct is grounded below 1/6*v cc to ensure that the bootstrap capacitor is charged when ct is brought back over 1/3*v cc . non - latched shutdown if ct is pulled down below v ctsd (approximately 1/6 of v cc ) by an external circuit, ct is not able to charge u p and oscillation stops. ho1 and ho2 outputs are held low . lo1 and lo2 outputs remain high while vct remains below v ct - enabling the bootstrap capacitors to charge. this state remains until the ct input is released and oscillation can resume. latched shutdown when the sd pin is brought above 2 v, the ic goes into fault mode and all outputs are low. v cc has to be recycled below v ccuv - to restart. the sd pin can be used for over - current or over - voltage protection using appropriate external circui try. ct rt f ? ? ? 453 . 1 1
ir s2453(1)d(s) 14 www.irf.com ? 20 12 international rectifier november 28 , 2012 deadtime waveform rise and fall time waveform t d _ h o 1 5 0 % 5 0 % 5 0 % 5 0 % h o 1 l o 1 t d _ l o 1 5 0 % t o n _ l o t r t f 90% 10% ho lo
ir s2453(1)d(s) 15 www.irf.com ? 20 12 international rectifier november 28 , 2012 package details
ir s2453(1)d(s) 16 www.irf.com ? 20 12 international rectifier november 28 , 2012 tape and reel details e f a c d g a b h note : controlling dim ension in m m loaded tape feed direction a h f e g d b c carrier tape dimension for 14soicn code min max min max a 7.90 8.10 0.311 0.318 b 3.90 4.10 0.153 0.161 c 15.70 16.30 0.618 0.641 d 7.40 7.60 0.291 0.299 e 6.40 6.60 0.252 0.260 f 9.40 9.60 0.370 0.378 g 1.50 n/a 0.059 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 14soicn code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 22.40 n/a 0.881 g 18.50 21.10 0.728 0.830 h 16.40 18.40 0.645 0.724 metric imperial
ir s2453(1)d(s) 17 www.irf.com ? 20 12 international rectifier november 28 , 2012 part marking information i r s 2 4 5 3 ( 1 ) d i r l o g o y w w ? p a r t n u m b e r d a t e c o d e p i n 1 i d e n t i f i e r l o t c o d e ( p r o d m o d e C 4 d i g i t s p n c o d e ) a s s e m b l y s i t e c o d e p e r s c o p 2 0 0 - 0 0 2 ? x x x x m a r k i n g c o d e l e a d f r e e r e l e a s e d n o n - l e a d f r e e r e l e a s e d ? p
ir s2453(1)d(s) 18 www.irf.com ? 20 12 international rectifier november 28 , 2012 the information provided in this document is believed to be accurate and reliable. however, international rectifier assumes no responsibility for the consequences of the use of this information. international rectifier assumes no responsibility for any in fringement of patents or of other rights of third parties which may result from the use of this information. no license is granted by implication or otherwise under any patent or patent rights of international rectifier. the specifications mentioned in t his document are subject to change without notice. this document supersedes and replaces all information previously supplied. for technical support, please contact irs technical assistance center htt p://www.irf.com/technical - info/ world headquarters: 101n sepulveda blvd ., el segundo, california 90245 tel: (310) 252 - 7105

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